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Journals
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T-ROEnabling Kubernetes Orchestration of Mixed-Criticality Software for Autonomous Mobile RobotsIEEE Transactions on Robotics, pp. 540-553, 2024
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TVLSIEnhancing Strong PUF Security With Nonmonotonic Response QuantizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 55-64, Jan, 2023
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TCOMPTask Mapping and Scheduling for OpenVX Applications on Heterogeneous Multi/Many-core ArchitecturesIEEE Transactions on Computers (TCOMP), pp. 1–14, Oct, 2021
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TACOGretch: A Hardware Prefetcher for Graph AnalyticsACM Transactions on Architecture and Code Optimization (TACO), pp. 1–25, Nov, 2020
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TCOMPDesigning Predictable Cache Coherence for Multi-core Real-Time SystemsIEEE Transactions on Computers (TCOMP), pp. 1–16, Nov, 2020
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TECSA Comparative Study of Predictable DRAM ControllersACM Transactions on Embedded Computing Systems (TECS), pp. 53:1–53:23, Nov, 2018
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TECSExposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based AnalysisACM Transactions on Embedded Computing Systems (TECS), pp. 90:1–90:25, Nov, 2018
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TCADMCXplore: Automating the Validation Process of DRAM Memory Controller DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1050–1063, Nov, 2018
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TECSPMC: A Requirement-aware DRAM Controller for Multi-core Mixed CriticalityACM Transactions on Embedded Computing Systems (TECS), pp. 100:1–100:28, May, 2017
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TODAESPath Selection for Real-Time Communication on Priority-Aware NoCsACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 53:1–53:25, Jul, 2016TCOMPSLA: A Stage-level Latency Analysis for Real-time Communication in a Pipelined Resource ModelIEEE Transactions on Computers (TCOMP), pp. 1177–1190, Apr, 2015DACReliable Computing with Ultra-Reduced Instruction Set Co-processorsIEEE Micro, pp. 86–94, Dec, 2014TCADAn Instruction Scratchpad Memory Allocation for the Precision Timed ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1819–1823, Nov, 2013TCADsynASM: A High-level Synthesis Framework that Supports Explicit Parallel and Timed ConstructsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1508–1521, Oct, 2012PERRobust Heterogeneous Data Center Design: A Principled ApproachACM SIGMETRICS Performance Evaluation Review (PER), pp. 28–30, Dec, 2011ENTCSGenerating Multi-threaded code from Polychronous SpecificationsElectronic Notes in Theoretical Computer Science, pp. 57–69, Jun, 2009DAESSML-Sys: A Functional Framework with Multiple Models of Computation for Modeling Heterogeneous SystemDesign Automation for Embedded Systems, pp. 1–30, Jun, 2008TODAESEWD: A Metamodeling Driven Customizable Multi-MoC System Modeling EnvironmentACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 1–43, May, 2008EURASIPModel-driven Validation of SystemC DesignsEURASIP Journal on Embedded Systems, pp. 1–14, Apr, 2008TCADOn Cosimulating Multiple Abstraction-Level System-Level ModelsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 394–398, Feb, 2008TCADHeterogeneous Behavioral Hierarchy Extensions for SystemCIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 765–780, Apr, 2007TCADCARH: A Service-oriented Architecture for Validating System-level DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1458–1474, Aug, 2006TCADTowards a Heterogeneous Simulation Kernel for System-level Models: A SystemC kernel for Synchronous Data Flow ModelsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1261–1271, Aug, 2005
Conferences
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IROSContainerization and Orchestration of Software for Autonomous Mobile Robots: a Case Study of Mixed-Criticality Tasks across Edge-Cloud Computing PlatformsIn IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pp. 1–7, Apr, 2022
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RTASA Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache CoherenceIn proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, May, 2021
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DACA Framework for Optimizing CPU-iGPU Communication on Embedded PlatformsIn proceedings of IEEE Design Automation Conference (DAC), pp. 685–690, Mar, 2021
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DATEOn the Task Mapping and Scheduling for DAG-based Embedded Vision Applications on Heterogeneous Multi/Many-core ArchitecturesIn proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 1003–1006, Mar, 2020
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RTSSCARP: A Data Communication Mechanism for Multi-Core Mixed-Criticality SystemsIn proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–11, Dec, 2019
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RTSSEnabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality SystemsIn proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–11, Dec, 2019
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ICCADStrengthening PUFs using CompositionIn proceedings of IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1–8, Nov, 2019
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IWOCLApplying Models of Computation to OpenCL Pipes for FPGA ComputingIn Proceedings of the 5th International Workshop on OpenCL, pp. 9:1–9:4, Apr, 2017
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DATEMCXplore: An Automated Framework for Validating Memory Controller DesignsIn proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 1357–1362, Sep, 2016
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RTASBuffer Space Allocation for Real-Time Priority-Aware NetworksIn proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 255–266, Apr, 2016
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RTASCriticality- and Requirement-aware Bus Arbitration for Multi-core Mixed Criticality SystemsIn proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 73–83, Apr, 2016
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RTASReverse-engineering Embedded Memory Controllers through Latency-based analysisIn proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 297–306, Dec, 2015
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RTASA Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical SystemsIn proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 307–316, Oct, 2015
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ETFAStatic slack-based instrumentation of programsIn 20th IEEE Conference on Emerging Technologies & Factory Automation, ETFA, pp. 1–8, Sep, 2015
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ASP-DACBounding Buffer Space Requirements for Real-Time Priority-Aware NetworksIn proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 113–118, Jul, 2014Best paper candidate.
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FDLsystemc-clang: An Open-source Framework for Analyzing Mixed-abstraction SystemC ModelsIn proceedings of IEEE Forum on Specification and Design Languages (FDL), pp. 1–8, Sep, 2013
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RTASORTAP: An Offset-based Response Time Analysis for a Pipelined Communication Resource ModelIn proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 247–258, Apr, 2013
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DATELow Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-ProcessorsIn proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 933–938, Mar, 2013
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DATEOn the Use of GP-GPUs for Accelerating Compute-intensive EDA ApplicationsIn proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 1357–1366, Mar, 2013
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HLDVTAccelerating SystemC Simulations using GPUsIn proceedings of IEEE International High Level Design Validation and Test Workshop (HLDVT), pp. 132–139, Nov, 2012ASP-DACUsing Link-level Latency Analysis for Path Selection for Real-time Communication on NoCsIn proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 499–504, Jul, 2012ASP-DACParallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUsIn proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 455–460, Jul, 2012DACReliable Computing with Ultra-Reduced Instruction-Set Co-processorsIn proceedings of IEEE Design Automation Conference (DAC), pp. 697–702, Jun, 2012DATEAn Instruction Scratchpad Memory Allocation for the Precision Timed ArchitectureIn proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 659–664, Mar, 2012CODESPRET DRAM Controller: On the Virtue of PrivitizationIn proceedings of ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES/ ISSS), pp. 99–108, Oct, 2011DACTemporal Isolation on Multiprocessing ArchitecturesIn proceedings of IEEE Design Automation Conference (DAC), pp. 274–279, Jun, 2011SACMATAn Authorization Scheme for Version Control SystemsIn proceedings of ACM Symposium on Access Control Models and Technologies (SACMAT), pp. 123–132, Jun, 2011ASPLOS-I&PA Case for Instruction Subset Architectures (I_SA) – Guaranteeing Functionality in High Defect Rate TechnologiesIn ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Session on Ideas and Perspectives, pp. 1–2, Mar, 2011FCCMAbstract State Machines as an Intermediate Representation for High Level SynthesisIn proceedings of IEEE Design, Automation and Test in Europe (DATE) , pp. 1–6, Mar, 2011MAMARobust Heterogeneous Data Center Design:A Principled ApproachIn proceedings of Workshop on Mathematical Performance Modeling and Analysis (MAMA), pp. 1–4, Mar, 2011FCCMExtending Force-directed Scheduling with Explicit Parallel and Timed Constructs for High-level SynthesisIn proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 214–217, Mar, 2011MTVA Hardware/Software Co-design Framework using Abstract State MachinesIn proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 53–58, Dec, 2010RTCSADeploying Hard Real-time Control Software on CMPsIn International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 283–292, Aug, 2010ASP-DACSCGPSim: A fast SystemC simulator on GPUsIn proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 149–154, Aug, 2010Best paper award.ICCDA Disruptive Computer Design Idea: Architectures with Repeatable TimingIn proceedings of IEEE International Conference on Computer Design (ICCD), pp. 54–59, Oct, 2009RTAS-POSTERPoster Abstract: Timing Instructions - ISA Extensions for Timing GuaranteesIn proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–2, Apr, 2009REPP-INVITEDReconciling repeatable timing with pipelining and memory hierarchyIn proceedings of the Workshop on Reconciling Performance with Predictability (RePP), pp. 1–6, Apr, 2009CASESPredictable Programming on a Precision Timed ArchitectureIn proceedings of International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), pp. 137-146, Oct, 2008DSRTAn Automated Mapping of Timed Functional Specification to A Precision Timed ArchitectureIn proceedings of the IEEE International Symposium on Distributed Simulation and Real Time Applications (DSRT), pp. 322–325, Oct, 2008MEMOCODEOn the Deterministic Multi-threaded Software Synthesis from Polychronous SpecificationsIn proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 129–138, Jun, 2008RTAS-WIPToward an Effective Execution Policy for Distributed Real-Time Embedded SystemsIn proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Work-in-Progress Session, pp. 1–4, Apr, 2008ASP-DACExploring Power Management in Multi-core SystemsIn proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 708-713, Mar, 2008DACModel-driven Validation of SystemC DesignsIn proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 29–34, Jun, 2007DATETackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESLIn proceedings of Design, Automation and Test in Europe Conference (DATE), pp. 279–284, May, 2007CODESPerformance modeling for early analysis of multi-core systemsIn proceedings of IEEE/ACM International Conference on Hardware/software Codesign and System Synthesis (CODES/ISSS), pp. 209–214, May, 2007Deep vs. Shallow, Kernel vs. Language–What is Better for Heterogeneous Modeling in SystemC?In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 68–75, Dec, 2006MEMOCODEA rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-designIn proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 39–48, Jul, 2006DATEHeterogeneous Behavioral Hierarchy for System Level DesignsIn proceedings of Design, Automation and Test in Europe (DATE), pp. 565–570, Mar, 2006MTVAutomated Extraction of Structural Information from SystemC-based IP for ValidationIn proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 99-104, Nov, 2005FDLSystemCXML: An extensible SystemC front end using XMLIn proceedings of Forum on Design and Specification Languages (FDL), pp. 405–409, Sep, 2005FDLTowards Behavioral Hierarchy Extensions for SystemCIn proceedings of Forum on Design and Specification Languages (FDL) , pp. 361–373, Sep, 2005FDLModeling environment for heterogeneous systems based on generic MoCsIn proceedings of Forum on Design and Specification Languages (FDL) , pp. 291–303, Sep, 2005GLSVLSITowards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow modelsIn proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 248–253, Feb, 2004ISVLSITowards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow ModelsIn proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 241–242, Feb, 2004FDLA Functional Programming Framework for Heterogeneous Models of Computation for System DesignIn proceedings of Forum on Specification and Design Languages (FDL), pp. 586–598, Feb, 2004MTVSystematic abstractions of microprocessor RTL models to enhance simulation efficiencyIn proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 103-108, May, 2003
Books
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SpringerLanguages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017 [Verona, Italy, September 18-20 , 2017], 2019
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SPRINGERIngredients for Successful System Level Design Methodology, pp. 208, Jun, 2008
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SPRINGERSystemC Kernel Extensions for Heterogeneous System Modeling, pp. 172, Jan, 2005
Book chapters
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CRCDesign Issues for Networked Embedded Systems, pp. 1–18, 2006
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FDLUMoC++: Modeling environment for heterogeneous systems based on generic MoCs, pp. 1–18, 2005
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CRCA survey of networked embedded systems: An introduction, pp. 1–18, 2004
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KLUWERTruly heterogeneous modeling with SystemC, pp. 88–101, 2004
Technical reports
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CAESR-TR-2019-01Technical Report: PENDULUM: A Cache Coherence Protocol for Mixed Criticality Systems, pp. 1–11, Dec, 2019
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CAESR-TR-2017-01Technical Report for HourGlass: Predictable Time-based Cache Coherence Protocol for Mixed-Time Critical Multi-Cores, pp. 1–8, Dec, 2017CAESR-TR-2012-05HolisticNoC: A NoC-Aware Holistic Analysis for Distributing Hard Real-time Systems on CMPs, pp. 1–7, Sep, 2012CAESR-TR-2012-05Accelerating SystemC Simulations using GPUs, pp. 132–139, Sep, 2012CAESR-TR-2012-03Reliable Computing with Ultra-Reduced Instruction-Set Co-processors, pp. 1–6, Mar, 2012CAESR-TR-2012-04An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture, pp. 1–6, Mar, 2012CAESR-TR-2012-02Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs, pp. 1–6, Jan, 2012CAESR-TR-2012-01Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs, pp. 1–6, Jan, 2012CUCS-038-09Using a Model Checker to Determine Worst-case Execution Time, pp. 1–6, Jan, 2009UCB/EECS-2008-115A Timing Requirements-Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture, pp. 1–6, Nov, 2008UCB/EECS-2008-104A Scratchpad Memory Allocation Scheme for Dataflow Models, pp. 1–6, Aug, 2008UCB/EECS-2008-72PTIDES: A Programming Model for Distributed Real-Time Embedded Systems, pp. 1–6, May, 2008