Hiren Patel

Publications

By Year By Type

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2024

T-RO

Enabling Kubernetes Orchestration of Mixed-Criticality Software for Autonomous Mobile Robots

Francesco Lumpp, Franco Fummi, Hiren D. Patel, and Nicola Bombieri

IEEE Transactions on Robotics, pp. 540-553, 2024

BIBTEX

@article{lumpp_24_trob,
  author = {Lumpp, Francesco and Fummi, Franco and Patel, Hiren D. and Bombieri, Nicola},
  journal = {IEEE Transactions on Robotics},
  title = {Enabling Kubernetes Orchestration of Mixed-Criticality Software for
             Autonomous Mobile Robots},
  abbr = {T-RO},
  year = {2024},
  volume = {40},
  number = {},
  pages = {540-553},
  public = {yes},
  bibtex_show = {yes},
  doi = {10.1109/TRO.2023.3334642}
}

RTAS

Exclusive Hierarchies for Predictable Sharing in Last-level Cache

Xinzhe Wang, Zhuanhao Wu, Rodolfo Pellizzoni, and Hiren Patel

In proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–-11, May, 2024

BIBTEX PDF

@inproceedings{wang_24_excl,
  author = {Wang, Xinzhe and Wu, Zhuanhao and Pellizzoni, Rodolfo and Patel, Hiren},
  booktitle = {{proceedings of IEEE Real-Time and Embedded Technology and
                 Applications Symposium (RTAS)}},
  pages = {1–-11},
  numpages = {11},
  publisher = {IEEE},
  month = may,
  abbr = {RTAS},
  title = {{Exclusive Hierarchies for Predictable Sharing in Last-level Cache}},
  pdf = {yes},
  public = {yes},
  bibtex_show = {yes},
  year = {2024}
}

DATE

A Compiler Phase to Optimally Split GPU Wavefronts for Safety-critical Systems

Artem Klashtorny, Mahesh Tripunitara, and Hiren Patel

In proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 1–-6, Mar, 2024

BIBTEX PDF

@inproceedings{klashtorny_24_optpws,
  author = {Klashtorny, Artem and Tripunitara, Mahesh and Patel, Hiren},
  booktitle = {{proceedings of IEEE Design Automation and Test in Europe (DATE)}
                 },
  pages = {1–-6},
  numpages = {6},
  publisher = {IEEE},
  month = mar,
  abbr = {DATE},
  title = {{A Compiler Phase to Optimally Split GPU Wavefronts for
             Safety-critical Systems}},
  public = {yes},
  pdf = {yes},
  bibtex_show = {yes},
  year = {2024}
}

2023

CASES/TECS

Predictable GPU Wavefront Splitting for Safety-Critical Systems

Artem Klashtorny, Zhuanhao Wu, Anirudh Mohan Kaushik, and Hiren Patel

ACM Trans. Embed. Comput. Syst., pp. 1–25, Sep, 2023

BIBTEX PDF

@article{klashtorny_23_pws,
  abbr = {CASES/TECS},
  author = {Klashtorny, Artem and Wu, Zhuanhao and Kaushik, Anirudh Mohan and Patel, Hiren},
  title = {Predictable GPU Wavefront Splitting for Safety-Critical Systems},
  year = {2023},
  issue_date = {October 2023},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  pages = {1--25},
  volume = {22},
  number = {5s},
  issn = {1539-9087},
  url = {https://doi.org/10.1145/3609102},
  doi = {10.1145/3609102},
  journal = {ACM Trans. Embed. Comput. Syst.},
  month = sep,
  articleno = {107},
  numpages = {25},
  keywords = {safety-critical systems, GPU},
  pdf = {yes},
  bibtex_show = {yes},
  public = {yes}
}

TVLSI

Enhancing Strong PUF Security With Nonmonotonic Response Quantization

Hugo Stangherlin, Zhuanhao Wu, Hiren Patel, and Manoj Sachdev

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 55-64, Jan, 2023

BIBTEX

@article{hugo_23_tvlsi,
  author = {Stangherlin, Hugo and Wu, Zhuanhao and Patel, Hiren and Sachdev, Manoj},
  journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  title = {Enhancing Strong PUF Security With Nonmonotonic Response Quantization
             },
  year = {2023},
  volume = {31},
  number = {01},
  issn = {1557-9999},
  pages = {55-64},
  keywords = {physical unclonable function;delays;quantization (signal);bit
                error rate;authentication;ring oscillators;resilience},
  doi = {10.1109/TVLSI.2022.3212271},
  publisher = {IEEE Computer Society},
  address = {Los Alamitos, CA, USA},
  month = jan,
  public = {yes},
  bibtex_show = {yes},
  abbr = {TVLSI}
}

RTAS

ZeroCost-LLC: Shared LLCs at No Cost to WCL

Zhuanhao Wu, Anirudh M. Kaushik, and Hiren Patel

In proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 249-261, May, 2023

BIBTEX PDF

@inproceedings{wu_23_zcllc_rtas,
  author = {Wu, Zhuanhao and Kaushik, Anirudh M. and Patel, Hiren},
  booktitle = {{proceedings of IEEE Real-Time and Embedded Technology and
                 Applications Symposium (RTAS)}},
  pages = {249-261},
  numpages = {11},
  publisher = {IEEE},
  month = may,
  abbr = {RTAS},
  title = {{ZeroCost-LLC: Shared LLCs at No Cost to WCL}},
  pdf = {yes},
  public = {yes},
  bibtex_show = {yes},
  year = {2023}
}

FCCM

SCCL: An open-source SystemC to RTL translator

Zhuanhao Wu, Maya Gokhale, Scott Lloyd, and Hiren Patel

In proceedings of International Symposium On Field-Programmable Custom Computing Machines (FCCM), pp. 23-33, May, 2023

BIBTEX PDF

@inproceedings{wu_23_sccl_fccm,
  author = {Wu, Zhuanhao and Gokhale, Maya and Lloyd, Scott and Patel, Hiren},
  booktitle = {{proceedings of International Symposium On Field-Programmable
                 Custom Computing Machines (FCCM)}},
  pages = {23-33},
  numpages = {10},
  publisher = {IEEE},
  month = may,
  abbr = {FCCM},
  title = {{SCCL: An open-source SystemC to RTL translator}},
  pdf = {yes},
  public = {yes},
  bibtex_show = {yes},
  year = {2023}
}

DATE

Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems

Zhuanhao Wu, Marat Bekmyrza, Nachiket Kapre, and Hiren Patel

In proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 1–-6, Apr, 2023

Nominated for best paper award.

BIBTEX PDF

@inproceedings{wu_23_ditty_date,
  author = {Wu, Zhuanhao and Bekmyrza, Marat and Kapre, Nachiket and Patel, Hiren},
  booktitle = {{proceedings of IEEE Design Automation and Test in Europe (DATE)}
                 },
  pages = {1–-6},
  numpages = {6},
  publisher = {IEEE},
  month = apr,
  abbr = {DATE},
  title = {{Ditty: Directory-based Cache Coherence for Multicore Safety-critical
             Systems}},
  award = {Nominated for best paper award.},
  pdf = {yes},
  public = {yes},
  bibtex_show = {yes},
  year = {2023}
}

TCRTS

PASoC: A Predictable Accelerator-Rich SoC

Susmita Tadepalli, Zhuanhao Wu, and Hiren Patel

In Proceedings of Cyber-Physical Systems and Internet of Things Week 2023, pp. 325–330, Apr, 2023

BIBTEX PDF

@inproceedings{tadepalli_23_pasoc,
  author = {Tadepalli, Susmita and Wu, Zhuanhao and Patel, Hiren},
  title = {PASoC: A Predictable Accelerator-Rich SoC},
  year = {2023},
  isbn = {9798400700491},
  publisher = {Association for Computing Machinery},
  address = {New York, NY, USA},
  url = {https://doi.org/10.1145/3576914.3587496},
  doi = {10.1145/3576914.3587496},
  booktitle = {Proceedings of Cyber-Physical Systems and Internet of Things Week
                 2023},
  pages = {325–330},
  numpages = {6},
  keywords = {Hardware accelerators, Safety-critical systems, Predictability,
                SoCs},
  location = {San Antonio, TX, USA},
  pdf = {yes},
  public = {yes},
  abbr = {TCRTS},
  bibtex_show = {yes},
  series = {CPS-IoT Week '23}
}

2022

TCAD

Automatic Construction of Predictable and High-Performance Cache Coherence Protocols for Multi-Core Real-Time Systems

Anirudh M. Kaushik, and Hiren Patel

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 14, Oct, 2022

IEEE Code

FPT

ZHW: A Numerical CODEC for Big Data Scientific Computation

Michael Barrow, Zhuanhao Wu, Scott Lloyd, Maya Gokhale, Hiren Patel, and Peter Lindstrom

In International Conference on Field-Programmable Technology (FPT), pp. 1-9, Oct, 2022

IEEE BIBTEX Code

@inproceedings{barrow_22_fpt,
  author = {Barrow, Michael and Wu, Zhuanhao and Lloyd, Scott and Gokhale, Maya and Patel, Hiren and Lindstrom, Peter},
  booktitle = {International Conference on Field-Programmable Technology (FPT)},
  title = {ZHW: A Numerical CODEC for Big Data Scientific Computation},
  year = {2022},
  abbr = {FPT},
  pages = {1-9},
  public = {yes},
  ieeelink = {https://ieeexplore.ieee.org/document/9974258},
  code = {https://github.com/LLNL/zhw},
  bibtex_show = {yes},
  doi = {10.1109/ICFPT56656.2022.9974258}
}

FCCM

Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs

Srinirdheeshwar Kuttuva Prakash, Hiren Patel, and Nachiket Kapre

In IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 1-9, Oct, 2022

IEEE BIBTEX

@inproceedings{prakash_22_hbm,
  author = {Prakash, Srinirdheeshwar Kuttuva and Patel, Hiren and Kapre, Nachiket},
  booktitle = {IEEE Annual International Symposium on Field-Programmable Custom
                 Computing Machines (FCCM)},
  title = {Managing HBM Bandwidth on Multi-Die FPGAs with FPGA Overlay NoCs},
  year = {2022},
  pages = {1-9},
  public = {yes},
  %pdf = {yes},
  abbr = {FCCM},
  ieeelink = {https://ieeexplore.ieee.org/document/9786203},
  bibtex_show = {yes},
  doi = {10.1109/FCCM53951.2022.9786203}
}

DAC

Predictable Sharing of Last-level Cache Partitions for Multi-core Safety-critical Systems

Zhuanhao Wu, and Hiren Patel

In proceedings of IEEE Design Automation Conference (DAC), pp. 1273–1278, Oct, 2022

PDF BIBTEX

@inproceedings{wu_22_llc_dac,
  author = {Wu, Zhuanhao and Patel, Hiren},
  booktitle = {{proceedings of IEEE Design Automation Conference (DAC)}},
  pages = {1273–1278},
  numpages = {6},
  public = {yes},
  publisher = {IEEE},
  abbr = {DAC},
  acmlink = {https://dl.acm.org/doi/abs/10.1145/3489517.3530614},
  title = {{Predictable Sharing of Last-level Cache Partitions for Multi-core
             Safety-critical Systems}},
  pdf = {yes},
  bibtex_show = {yes},
  year = {2022}
}

IROS

Containerization and Orchestration of Software for Autonomous Mobile Robots: a Case Study of Mixed-Criticality Tasks across Edge-Cloud Computing Platforms

Francesco Lumpp, Franco Fummi, Hiren Patel, and Nicola Bombieri

In IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), pp. 1–7, Oct, 2022

2021

TCOMP

Task Mapping and Scheduling for OpenVX Applications on Heterogeneous Multi/Many-core Architectures

Francesco Lumpp, Stefano Aldeheri, Hiren Patel, and Nicola Bombieri

IEEE Transactions on Computers (TCOMP), pp. 1–14, Oct, 2021

IEEE

RTAS

A Hardware Platform for Exploring Predictable Cache Coherence Protocols for Real-time Multicores

Zhuanhao Wu, Anirudh M. Kaushik, and Hiren Patel

In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, May, 2021

IEEE PDF Code
RTAS

A Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache Coherence

Anirudh M. Kaushik, and Hiren Patel

In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–12, May, 2021

IEEE
DATE

Automated Synthesis of Predictable and High-Performance Cache Coherence Protocols

Anirudh M. Kaushik, and Hiren Patel

In proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 1–6, Mar, 2021

IEEE PDF Code
DAC

A Framework for Optimizing CPU-iGPU Communication on Embedded Platforms

Francesco Lumpp, Hiren Patel, and Nicola Bombieri

In proceedings of IEEE Design Automation Conference (DAC), pp. 685–690, Mar, 2021

PDF

2020

TACO

Gretch: A Hardware Prefetcher for Graph Analytics

Anirudh M. Kaushik, Gennady Pekhimenko, and Hiren Patel

ACM Transactions on Architecture and Code Optimization (TACO), pp. 1–25, Nov, 2020

PDF
TCOMP

Designing Predictable Cache Coherence for Multi-core Real-Time Systems

Anirudh M. Kaushik, Mohamed Hassan, and Hiren Patel

IEEE Transactions on Computers (TCOMP), pp. 1–16, Nov, 2020

Code

DATE

On the Task Mapping and Scheduling for DAG-based Embedded Vision Applications on Heterogeneous Multi/Many-core Architectures

Stefano Aldegheri, Nicola Bombieri, and Hiren Patel

In proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 1003–1006, Mar, 2020

2019

Springer

Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017 [Verona, Italy, September 18-20 , 2017]

, pp. 1003–1006, Mar, 2019

RTSS

CARP: A Data Communication Mechanism for Multi-Core Mixed-Criticality Systems

Anirudh M. Kaushik, Paulos Tegegn, Zhuanhao Wu, and Hiren Patel

In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–11, Dec, 2019

PDF
RTSS

Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems

Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan, and Hiren Patel

In proceedings of IEEE Real-Time Systems Symposium (RTSS), pp. 1–11, Dec, 2019
ICCAD

Strengthening PUFs using Composition

Zhuanhao Wu, Hiren Patel, Manoj Sachdev, and Mahesh Tripunitara

In proceedings of IEEE/ACM International Conference On Computer Aided Design (ICCAD), pp. 1–8, Nov, 2019

PDF

CAESR-TR-2019-01

Technical Report: PENDULUM: A Cache Coherence Protocol for Mixed Criticality Systems

Nivedita Sritharan, Anirudh M. Kaushik, Mohamed Hassan, and Hiren Patel

, pp. 1–11, Dec, 2019

2018

TECS

A Comparative Study of Predictable DRAM Controllers

Danlu Guo, Mohamed Hassan, Rodolfo Pellizzoni, and Hiren Patel

ACM Transactions on Embedded Computing Systems (TECS), pp. 53:1–53:23, Nov, 2018
TECS

Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis

Mohamed Hassan, Anirudh M. Kaushik, and Hiren Patel

ACM Transactions on Embedded Computing Systems (TECS), pp. 90:1–90:25, Nov, 2018
TCAD

MCXplore: Automating the Validation Process of DRAM Memory Controller Designs

Mohamed Hassan, and Hiren Patel

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1050–1063, Nov, 2018

2017

TECS

PMC: A Requirement-aware DRAM Controller for Multi-core Mixed Criticality

Mohamed Hassan, Hiren Patel, and Rodolfo Pellizzoni

ACM Transactions on Embedded Computing Systems (TECS), pp. 100:1–100:28, May, 2017

RTAS

Predictable cache coherence for multi-core real time systems

Mohamed Hassan, Anirudh M. Kaushik, and Hiren Patel

In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 235–246, Apr, 2017

PDF Code
IWOCL

Applying Models of Computation to OpenCL Pipes for FPGA Computing

Nachiket Kapre, and Hiren Patel

In Proceedings of the 5th International Workshop on OpenCL, pp. 9:1–9:4, Apr, 2017

CAESR-TR-2017-01

Technical Report for HourGlass: Predictable Time-based Cache Coherence Protocol for Mixed-Time Critical Multi-Cores

Nividita Sritharan, Anirudh Kaushik, Mohamed Hassan, and Hiren Patel

, pp. 1–8, Dec, 2017

2016

TODAES

Path Selection for Real-Time Communication on Priority-Aware NoCs

Hany Kashif, Hiren Patel, and Sebastian Fischmeister

ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 53:1–53:25, Jul, 2016

DATE

MCXplore: An Automated Framework for Validating Memory Controller Designs

Mohamed Hassan, and Hiren Patel

In proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 1357–1362, Sep, 2016

Code
RTAS

Buffer Space Allocation for Real-Time Priority-Aware Networks

Hany Kashif, and Hiren Patel

In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 255–266, Apr, 2016
RTAS

Criticality- and Requirement-aware Bus Arbitration for Multi-core Mixed Criticality Systems

Mohamed Hassan, and Hiren Patel

In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 73–83, Apr, 2016

2015

TCOMP

SLA: A Stage-level Latency Analysis for Real-time Communication in a Pipelined Resource Model

Hany Kashif, Sina Gholamian, and Hiren Patel

IEEE Transactions on Computers (TCOMP), pp. 1177–1190, Apr, 2015

RTAS

Reverse-engineering Embedded Memory Controllers through Latency-based analysis

Mohamed Hassan, Anirudh M. Kaushik, and Hiren Patel

In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 297–306, Dec, 2015
RTAS

A Framework for Scheduling DRAM Memory Accesses for Multi-Core Mixed-time Critical Systems

Mohamed Hassan, Hiren Patel, and Rodolfo Pellizzoni

In proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 307–316, Oct, 2015
ETFA

Static slack-based instrumentation of programs

Hany Kashif, Johnson J. Thomas, Hiren Patel, and Sebastian Fischmeister

In 20th IEEE Conference on Emerging Technologies & Factory Automation, ETFA, pp. 1–8, Sep, 2015

2014

DAC

Reliable Computing with Ultra-Reduced Instruction Set Co-processors

Dan Wang, Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren Patel, Mahesh V. Tripunitara, and Siddharth Garg

IEEE Micro, pp. 86–94, Dec, 2014

ASP-DAC

Bounding Buffer Space Requirements for Real-Time Priority-Aware Networks

Hany Kashif, and Hiren Patel

In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 113–118, Jul, 2014
Best paper candidate.

2013

TCAD

An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture

Aayush Prakash, and Hiren Patel

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1819–1823, Nov, 2013

FDL

systemc-clang: An Open-source Framework for Analyzing Mixed-abstraction SystemC Models

Anirudh M. Kaushik, and Hiren Patel

In proceedings of IEEE Forum on Specification and Design Languages (FDL), pp. 1–8, Sep, 2013
RTAS

ORTAP: An Offset-based Response Time Analysis for a Pipelined Communication Resource Model

Hany Kashif, Sina Gholamian, Rodolfo Pellizzoni, Hiren Patel, and Sebastian Fischmeister

In proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 247–258, Apr, 2013
DATE

Low Cost Permanent Fault Detection Using Ultra-Reduced Instruction Set Co-Processors

Sundaram Ananthanarayanan, Siddharth Garg, and Hiren Patel

In proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 933–938, Mar, 2013
DATE

On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications

Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, Anirudh M. Kaushik, and Hiren Patel

In proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 1357–1366, Mar, 2013

2012

TCAD

synASM: A High-level Synthesis Framework that Supports Explicit Parallel and Timed Constructs

Rohit Sinha, and Hiren Patel

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1508–1521, Oct, 2012

HLDVT

Accelerating SystemC Simulations using GPUs

Mahesh Nanjundappa, Anirudh M. Kaushik, Hiren Patel, and Sandeep K. Shukla

In proceedings of IEEE International High Level Design Validation and Test Workshop (HLDVT), pp. 132–139, Nov, 2012
ASP-DAC

Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs

Hany Kashif, Hiren Patel, and Sebastian Fischmeister

In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 499–504, Jul, 2012
ASP-DAC

Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs

Rohit Sinha, Aayush Prakash, and Hiren Patel

In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 455–460, Jul, 2012
DAC

Reliable Computing with Ultra-Reduced Instruction-Set Co-processors

Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren Patel, Mahesh V. Tripunitara, and Siddharth Garg

In proceedings of IEEE Design Automation Conference (DAC), pp. 697–702, Jun, 2012

PDF
DATE

An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture

Aayush Prakash, and Hiren Patel

In proceedings of IEEE Design Automation and Test in Europe (DATE) , pp. 659–664, Mar, 2012

CAESR-TR-2012-05

HolisticNoC: A NoC-Aware Holistic Analysis for Distributing Hard Real-time Systems on CMPs

Sina Gholamian, Hany Kashif, Hiren Patel, Rodolfo Pellizzoni, and Sebastian Fischmeister

, pp. 1–7, Sep, 2012
CAESR-TR-2012-05

Accelerating SystemC Simulations using GPUs

Mahesh Nanjundappa, Anirudh M. Kaushik, Hiren Patel, and Sandeep K. Shukla

, pp. 132–139, Sep, 2012
CAESR-TR-2012-03

Reliable Computing with Ultra-Reduced Instruction-Set Co-processors

Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren Patel, Mahesh V. Tripunitara, and Siddharth Garg

, pp. 1–6, Mar, 2012
CAESR-TR-2012-04

An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture

Aayush Prakash, and Hiren Patel

, pp. 1–6, Mar, 2012
CAESR-TR-2012-02

Using Link-level Latency Analysis for Path Selection for Real-time Communication on NoCs

Hany Kashif, Hiren Patel, and Sebastian Fischmeister

, pp. 1–6, Jan, 2012
CAESR-TR-2012-01

Parallel Simulation of Mixed-abstraction SystemC Models on GPUs and Multicore CPUs

Rohit Sinha, Aayush Prakash, and Hiren Patel

, pp. 1–6, Jan, 2012

2011

PER

Robust Heterogeneous Data Center Design: A Principled Approach

Siddharth Garg, Shreyas Sundaram, and Hiren Patel

ACM SIGMETRICS Performance Evaluation Review (PER), pp. 28–30, Dec, 2011

CODES

PRET DRAM Controller: On the Virtue of Privitization

Jan Reineke, Isaac Liu, Hiren Patel, Sungjun Kim, and Edward A. Lee

In proceedings of ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES/ ISSS), pp. 99–108, Oct, 2011
DAC

Temporal Isolation on Multiprocessing Architectures

Dai Bui, Edward A. Lee, Isaac Liu, Hiren Patel, and Jan Reineke

In proceedings of IEEE Design Automation Conference (DAC), pp. 274–279, Jun, 2011
SACMAT

An Authorization Scheme for Version Control Systems

Sitaram Chamarty, Hiren Patel, and Mahesh V. Tripunitara

In proceedings of ACM Symposium on Access Control Models and Technologies (SACMAT), pp. 123–132, Jun, 2011
ASPLOS-I&P

A Case for Instruction Subset Architectures (I_SA) – Guaranteeing Functionality in High Defect Rate Technologies

Hiren Patel, and Siddharth Garg

In ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Session on Ideas and Perspectives, pp. 1–2, Mar, 2011
FCCM

Abstract State Machines as an Intermediate Representation for High Level Synthesis

Rohit Sinha, and Hiren Patel

In proceedings of IEEE Design, Automation and Test in Europe (DATE) , pp. 1–6, Mar, 2011
MAMA

Robust Heterogeneous Data Center Design:A Principled Approach

Siddharth Garg, Shreyas Sundaram, and Hiren Patel

In proceedings of Workshop on Mathematical Performance Modeling and Analysis (MAMA), pp. 1–4, Mar, 2011
FCCM

Extending Force-directed Scheduling with Explicit Parallel and Timed Constructs for High-level Synthesis

Rohit Sinha, and Hiren Patel

In proceedings of IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 214–217, Mar, 2011

2010

MTV

A Hardware/Software Co-design Framework using Abstract State Machines

Nathan Buchanan, and Hiren Patel

In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 53–58, Dec, 2010
RTCSA

Deploying Hard Real-time Control Software on CMPs

Dai Bui, Hiren Patel, and Edward A. Lee

In International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp. 283–292, Aug, 2010
ASP-DAC

SCGPSim: A fast SystemC simulator on GPUs

Mahesh Nanjundappa, Hiren Patel, Bijoy A. Jose, and Sandeep K. Shukla

In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 149–154, Aug, 2010
Best paper award.

2009

ENTCS

Generating Multi-threaded code from Polychronous Specifications

Bijoy A. Jose, Hiren Patel, Sandeep K. Shukla, and Jean-Pierre Talpin

Electronic Notes in Theoretical Computer Science, pp. 57–69, Jun, 2009

ICCD

A Disruptive Computer Design Idea: Architectures with Repeatable Timing

Stephen A. Edwards, Sungjun Kim, Edward A. Lee, Isaac Liu, Hiren Patel, and Martin Schoeberl

In proceedings of IEEE International Conference on Computer Design (ICCD), pp. 54–59, Oct, 2009
RTAS-POSTER

Poster Abstract: Timing Instructions - ISA Extensions for Timing Guarantees

Isaac Liu, Ben Lickly, Hiren Patel, and Edward A. Lee

In proceedings of IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp. 1–2, Apr, 2009
REPP-INVITED

Reconciling repeatable timing with pipelining and memory hierarchy

Stephen A. Edward, Sungjun Kim, Edward A. Lee, Hiren Patel, and Martin Schoeberl

In proceedings of the Workshop on Reconciling Performance with Predictability (RePP), pp. 1–6, Apr, 2009

CUCS-038-09

Using a Model Checker to Determine Worst-case Execution Time

Sungjun Kim, Hiren Patel, and Stephen A. Edwards

, pp. 1–6, Apr, 2009

2008

DAES

SML-Sys: A Functional Framework with Multiple Models of Computation for Modeling Heterogeneous System

Deepak A. Mathaikutty, Hiren Patel, Sandeep K. Shukla, and Axel Jantsch

Design Automation for Embedded Systems, pp. 1–30, Jun, 2008
TODAES

EWD: A Metamodeling Driven Customizable Multi-MoC System Modeling Environment

Deepak A. Mathaikutty, Hiren Patel, Sandeep K. Shukla, and Axel Jantsch

ACM Transactions on Design Automation of Electronic Systems (TODAES), pp. 1–43, May, 2008
EURASIP

Model-driven Validation of SystemC Designs

Hiren Patel, and Sandeep K. Shukla

EURASIP Journal on Embedded Systems, pp. 1–14, Apr, 2008
TCAD

On Cosimulating Multiple Abstraction-Level System-Level Models

Hiren Patel, and Sandeep K. Shukla

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 394–398, Feb, 2008

SPRINGER

Ingredients for Successful System Level Design Methodology

Hiren Patel, and Sandeep K. Shukla

, pp. 208, Jun, 2008

CASES

Predictable Programming on a Precision Timed Architecture

Ben Lickly, Isaac Liu, Sungjun Kim, Hiren Patel, Stephen A. Edwards, and Edward A. Lee

In proceedings of International Conference on Compilers, Architecture, and Synthesis from Embedded Systems (CASES), pp. 137-146, Oct, 2008
DSRT

An Automated Mapping of Timed Functional Specification to A Precision Timed Architecture

Shanna-Shaye Forbes, Hugo Andrade, Hiren Patel, and Edward A. Lee

In proceedings of the IEEE International Symposium on Distributed Simulation and Real Time Applications (DSRT), pp. 322–325, Oct, 2008
MEMOCODE

On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications

Bijoy A. Jose, Sandeep K. Shukla, Hiren Patel, and Jean-Pierre Talpin

In proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 129–138, Jun, 2008
RTAS-WIP

Toward an Effective Execution Policy for Distributed Real-Time Embedded Systems

Thomas Huining Feng, Edward A. Lee, Hiren Patel, and Jia Zou

In proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Work-in-Progress Session, pp. 1–4, Apr, 2008
ASP-DAC

Exploring Power Management in Multi-core Systems

Reinaldo A. Bergamaschi, Guoling Han, A. Buyuktosunoglu, Hiren Patel, I. Nair, G. Dittmann, G. Janssen, N. Dhanwada, Zhigang Hu, P. Bose, and J. Darringer

In proceedings of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 708-713, Mar, 2008

UCB/EECS-2008-115

A Timing Requirements-Aware Scratchpad Memory Allocation Scheme for a Precision Timed Architecture

Hiren Patel, Ben Lickly, Bas Burgers, and Edward A. Lee

, pp. 708-713, Nov, 2008
UCB/EECS-2008-104

A Scratchpad Memory Allocation Scheme for Dataflow Models

Shamik Bandyopadhyay, Thomas Huining Feng, Hiren Patel, and Edward A. Lee

, pp. 708-713, Aug, 2008
UCB/EECS-2008-72

PTIDES: A Programming Model for Distributed Real-Time Embedded Systems

Patricia Derler, Thomas Huining Feng, Edward A. Lee, Slobodan Matic, Hiren Patel, Yang Zhao, and Jia Zou

, pp. 708-713, May, 2008

2007

TCAD

Heterogeneous Behavioral Hierarchy Extensions for SystemC

Hiren Patel, Sandeep K. Shukla, and Reinaldo A. Bergamaschi

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 765–780, Apr, 2007

DAC

Model-driven Validation of SystemC Designs

Hiren Patel, and Sandeep K. Shukla

In proceedings of ACM/IEEE Design Automation Conference (DAC), pp. 29–34, Jun, 2007
DATE

Tackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESL

Hiren Patel, and Sandeep K. Shukla

In proceedings of Design, Automation and Test in Europe Conference (DATE), pp. 279–284, May, 2007
CODES

Performance modeling for early analysis of multi-core systems

Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren Patel, Geert Janssen, Nagu Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-joon Nam, Dorothy Kucar, Pradip Bose, John Darringer, and Gualing Han

In proceedings of IEEE/ACM International Conference on Hardware/software Codesign and System Synthesis (CODES/ISSS), pp. 209–214, May, 2007

2006

TCAD

CARH: A Service-oriented Architecture for Validating System-level Designs

Hiren Patel, Deepak A. Mathaikutty, David Berner, and Sandeep K. Shukla

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1458–1474, Aug, 2006

Deep vs. Shallow, Kernel vs. Language–What is Better for Heterogeneous Modeling in SystemC?

Hiren Patel, and Sandeep K. Shukla

In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 68–75, Dec, 2006
MEMOCODE

A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design

Hiren Patel, Sandeep K. Shukla, Elliot Mednick, and Rishiyur S. Nikhil

In proceedings of ACM/IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), pp. 39–48, Jul, 2006
DATE

Heterogeneous Behavioral Hierarchy for System Level Designs

Hiren Patel, Sandeep K. Shukla, and Reinaldo A. Bergamaschi

In proceedings of Design, Automation and Test in Europe (DATE), pp. 565–570, Mar, 2006

CRC

Design Issues for Networked Embedded Systems

Hiren Patel, Sumit Gupta, Sandeep K. Shukla, and Rajesh Gupta

, pp. 1–18, Mar, 2006

2005

TCAD

Towards a Heterogeneous Simulation Kernel for System-level Models: A SystemC kernel for Synchronous Data Flow Models

Hiren Patel, and Sandeep K. Shukla

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 1261–1271, Mar, 2005

SPRINGER

SystemC Kernel Extensions for Heterogeneous System Modeling

Hiren Patel, and Sandeep K. Shukla

, pp. 172, Jan, 2005

MTV

Automated Extraction of Structural Information from SystemC-based IP for Validation

David Berner, Hiren Patel, Deepak A. Mathaikutty, and Sandeep K. Shukla

In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 99-104, Nov, 2005
FDL

SystemCXML: An extensible SystemC front end using XML

David Berner, Hiren Patel, Deepak A. Mathaikutty, Jean-Pierre Talpin, and Sandeep K. Shukla

In proceedings of Forum on Design and Specification Languages (FDL), pp. 405–409, Sep, 2005
FDL

Towards Behavioral Hierarchy Extensions for SystemC

Hiren Patel, and Sandeep K. Shukla

In proceedings of Forum on Design and Specification Languages (FDL) , pp. 361–373, Sep, 2005
FDL

Modeling environment for heterogeneous systems based on generic MoCs

Deepak A. Mathaikutty, Hiren Patel, Sandeep K. Shukla, and Axel Jantsch

In proceedings of Forum on Design and Specification Languages (FDL) , pp. 291–303, Sep, 2005

FDL

UMoC++: Modeling environment for heterogeneous systems based on generic MoCs

Deepak A. Mathaikutty, Hiren Patel, Sandeep K. Shukla, and Axel Jantsch

, pp. 291–303, Sep, 2005

2004

GLSVLSI

Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models

Hiren Patel, and Sandeep K. Shukla

In proceedings of IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 248–253, Feb, 2004
ISVLSI

Towards a Heterogeneous Simulation Kernel for System Level Models: A SystemC Kernel for Synchronous Data Flow Models

Hiren Patel, and Sandeep K. Shukla

In proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 241–242, Feb, 2004
FDL

A Functional Programming Framework for Heterogeneous Models of Computation for System Design

Deepak A. Mathaikutty, Hiren Patel, and Sandeep K. Shukla

In proceedings of Forum on Specification and Design Languages (FDL), pp. 586–598, Feb, 2004

CRC

A survey of networked embedded systems: An introduction

Hiren Patel, Sumit Gupta, Sandeep K. Shukla, and Rajesh Gupta

, pp. 586–598, Feb, 2004
KLUWER

Truly heterogeneous modeling with SystemC

Hiren Patel, and Sandeep K. Shukla

, pp. 88–101, Feb, 2004

2003

MTV

Systematic abstractions of microprocessor RTL models to enhance simulation efficiency

Debayan Bhaduri, Madhup Chandra, Hiren Patel, Shekhar Sharad, and Syed Suhaib

In proceedings of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp. 103-108, May, 2003